In the following description the term MOS is used to denote any FET or MIS transistor, half-transistor or capacitor structure. In order to simplify the description of the embodiments, references to gate oxides from this point forward should be understood to include dielectric materials, oxide, or a combination of oxide and dielectric materials.
Over the past 30 years, anti-fuse technology has attracted significant attention of many inventors, IC designers and manufacturers. An anti-fuse is a structure alterable to a conductive state, or in other words, an electronic device that changes state from not conducting to conducting. Equivalently, the binary states can be either one of high resistance and low resistance in response to electric stress, such as a programming voltage or current. Anti-fuse devices can be arranged into a memory array, thereby forming what is commonly known as a one-time-programmable (OTP) memory.
Current anti-fuse development is concentrated around 3-dimensional thin film structures and special inter-metal materials. Such anti-fuse technologies require additional processing steps not available in standard CMOS process, prohibiting anti-fuse applications in typical VLSI and ASIC designs, where programmability could help overcome problems with ever shrinking device life cycles and constantly rising chip development costs. Therefore there is an apparent need in the industry for a reliable anti-fuse structures utilizing standard CMOS process.
One type of anti-fuse memory cell manufacturable with a standard CMOS process is disclosed in U.S. Pat. No. 6,667,902 (Peng). Peng attempts to improve a classic planar DRAM-like anti-fuse array by introducing “row program lines” which connect to the capacitors and run parallel to the word lines. If decoded, the row program lines can minimize exposure of access transistors to a high programming voltage, which would otherwise occur through already programmed cells. Peng further improves his array in U.S. Pat. No. 6,671,040 by adding a variable voltage controlling programming current, which allegedly controls the degree of gate oxide breakdown, allowing for multilevel or analog storage applications.
FIG. 1 is a circuit diagram of an anti-fuse memory cell disclosed in Peng, while FIGS. 2 and 3 show simplified planar and cross-sectional views respectively of the anti-fuse memory cell shown in FIG. 1. The anti-fuse memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. Anti-fuse device 12 is considered a gate dielectric breakdown based anti-fuse devices. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses should be reliable while simple to manufacture with a low cost CMOS process.
The gate dielectric breakdown based anti-fuse devices are gaining popularity as a preferred OTP or emulated multiple time programmable (MTP) non-volatile memory devices in the industry. Such anti-fuse devices used either in a memory array or as an individual programmable cell consists of at least two regions. First is a high voltage breakdown region and second is a low voltage breakdown region (or anti-fuse region).
FIG. 4 is a cross sectional diagram of an improved version of the anti-fuse memory cell shown in FIG. 1. Just like the anti-fuse memory cell of FIG. 1, FIG. 4 shows a two-transistor anti-fuse memory cell 30, which consists of an access transistor in series with an anti-fuse device. The access transistor, or access device, includes a polysilicon gate 32 overlying a thick gate oxide 34, which itself is formed over the channel 36. On the left side of the channel 36 is a diffusion region 38 electrically connected to a bitline contact 40. On the right side of the channel 36 is a common diffusion region 42 shared with the anti-fuse device. The anti-fuse device includes a polysilicon gate 44 overlying a thin gate oxide 46, which itself is formed over the channel 48. The thick gate oxide 34 can correspond to that used for high voltage transistors while the thin gate oxide 46 can correspond to that used for low voltage transistors. Polysilicon gates 32 and 44 can be independently controlled, or alternatively can be connected to each other. For example, polysilicon gate 32 can be coupled to a wordline while polysilicon gate 44 can be coupled to a controlled cell plate voltage (VCP). Both diffusion regions 38 and 42 can have LDD regions, which can be identically doped or differently doped, depending on the desired operating voltages to be used. Thick field oxide, or shallow trench isolation (STI) oxide 54 and 56 are formed for isolating the memory cell from other memory cells and/or core circuitry transistors. Commonly owned U.S. 2007/0257331 filed on Jun. 13, 2007 describes alternate two-transistor anti-fuse memory cells which can be used in a non-volatile memory array. The thin gate oxide 46 is intended to breakdown in the presence of a large electrical field during a programming operation, thereby creating an electrically conductive connection between channel 48 and polysilicon gate 44. This electrically conductive connection can be referred to as a conductive link or anti-fuse.
Such an anti-fuse device implemented in a standard CMOS process utilizes high voltage (HV) or input/output (I/O) transistors and low voltage (LV) or core transistors to implement the thick dielectric and thin dielectric regions respectively. The fabrication of HV and LV transistors includes the process steps such as well formation and threshold voltage (Vt) adjustment implants. Those skilled in the art will understand that HV transistors are typically used in the I/O circuits such as input and output buffers, or in the circuitry that requires lower leakage and/or higher operating voltage comparing to the core area, where the LV transistors can be used. LV transistors on the other hand are typically used for core circuit transistors, or for circuitry that requires high speed switching performance for example. Accordingly, the electrical characteristics of HV and LV transistors are different since they are designed for specific applications. In the two-transistor anti-fuse memory cell 30, it is desirable to minimize the Vt of the anti-fuse device consisting of polysilicon gate 44. Therefore it is formed using an LV transistor process. As shown in FIG. 4 by example, the anti-fuse device consisting of polysilicon gate 44 is formed in a low voltage p-type well (PWELL-LV) 50 that has a dopant concentration, a Vt implant and gate oxide thickness specifically set for an LV transistor. The access device consisting of polysilicon gate 32 is formed in a high voltage p-type well (PWELL-HV) 52 that has a dopant concentration, a Vt implant and a gate oxide thickness specifically set for an HV transistor. Therefore the Vt of the anti-fuse device will be the same as the Vt of a core circuit transistor.
A driving factor for reducing cost of any memory is the memory array area. The two-transistor anti-fuse memory cell 30 of FIG. 4 is a relatively large memory cell when compared to single transistor memory cells, such as flash memory cells for example. A single transistor anti-fuse memory cell is described in commonly owned U.S. Pat. No. 7,402,855.
FIG. 5 is a cross-sectional view of the single transistor anti-fuse memory cell disclosed in commonly owned U.S. Pat. No. 7,402,85 5. Anti-fuse device 60 includes a variable thickness gate oxide 62 formed on the substrate channel region 64, a polysilicon gate 66, sidewall spacers 68, a field oxide region 70 a diffusion region 72, and an LDD region 74 in the diffusion region 72. A bitline contact 76 is shown to be in electrical contact with diffusion region 72. The variable thickness gate oxide 62 consists of a thick gate oxide and a thin gate oxide such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. From this point forward, the thin gate oxide portion corresponds to the anti-fuse device portion of the single transistor anti-fuse memory cell while the thick gate oxide portion corresponds to the access transistor or device portion of the single transistor anti-fuse memory cell. Generally, the thin gate oxide is a region where oxide breakdown can occur. The thick gate oxide edge meeting diffusion region 72 on the other hand, defines an access edge where gate oxide breakdown is prevented and current between the gate 66 and diffusion region 72 is to flow for a programmed anti-fuse device. While the distance that the thick oxide portion extends into the channel region depends on the mask grade, the thick oxide portion is preferably formed to be at least as long as the minimum length of a high voltage transistor formed on the same chip.
In the presently shown example, the diffusion region 72 is connected to a bitline through a bitline contact 76, or other line for sensing a current from the polysilicon gate 66, and can be doped to accommodate programming voltages or currents. This diffusion region 72 is formed proximate to the thick oxide portion of the variable thickness gate oxide 62. To further protect the edge of anti-fuse device 60 from high voltage damage, or current leakage, a resistor protection oxide (RPO), also known as a salicide protect oxide, can be introduced during the fabrication process to further space metal particles from the edge of sidewall spacer 68. This RPO is preferably used during the salicidation process for preventing only a portion of diffusion region 72 and a portion of polysilicon gate 66 from being salicided. It is well known that salicided transistors are known to have higher leakage and therefore lower breakdown voltage. Thus having a non-salicided diffusion region 72 will reduce leakage. Diffusion region 72 can be doped for low voltage transistors or high voltage transistors or a combination of the two resulting in same or different diffusion profiles.
Once again, it is desirable to minimize the Vt of the anti-fuse device defined by the portion of the polysilicon gate 66 over the thin gate oxide portion of the variable thickness gate oxide 62. Therefore it is formed using an LV transistor process. As shown in FIG. 5 by example, the anti-fuse device consisting of polysilicon gate 66 over the thin gate oxide portion is formed in a low voltage p-type well PWELL-LV 78 that has a dopant concentration, a Vt implant and gate oxide thickness specifically set for an LV transistor. The access gate consisting of polysilicon gate 66 over the thick gate oxide portion of the variable thickness gate oxide 62 is formed in a high voltage p-type well PWELL-HV 80 that has a dopant concentration, a Vt implant and a gate oxide thickness specifically set for an HV transistor. Therefore the Vt of the anti-fuse device will be the same as the Vt of a core circuit transistor.
Unfortunately, foundries for manufacturing semiconductor devices may have set types of LV transistor processes for manufacturing core circuits of the memory device, where the Vt control implant differs depending on the circuit application or function. Semiconductor memory devices generally have three circuit areas. First are the I/O circuits that are connected to pins of the package of the semiconductor memory device. Second are the core circuits, which include any logic and control circuits for example. Third is the memory array, which includes memory cells. Compounding this problem is the fact that the anti-fuse is typically designed on the basis of a particular LV transistor process, which means that the anti-fuse device has been qualified to operate properly if manufactured according to that particular LV transistor process. If the foundry does not have an LV transistor process suited for the design, then redesign of the anti-fuse device is required in order to qualify it for the available process. Such redesign incurs significant cost overhead, which is necessitated again when the foundry introduces a new generation of the process to accommodate a new manufacturing technology node. For example, an LV process for a 45 nm technology node may be different than that of a 20 nm technology node.
Another important issue is reliability of the anti-fuse memory device, and more specifically the quality of the thin gate oxide. The thin gate oxide quality is affected by the condition of the underlying channel surface, the concentration and uniformity of dopants at the channel surface, and implantation damage, just to name a few factors. Generally, the more process steps that the anti-fuse device is subjected to, the higher the probability for producing a defective anti-fuse device. Since anti-fuse based memory devices are programmed after manufacture by end-users, it is difficult to test for the reliability of an anti-fuse device before programming. Therefore the quality of the thin gate oxide should be maximized, since an inadvertently programmed anti-fuse device or an unprogrammable anti-fuse device will likely cause failure in the system. In the automotive industry, such a failure can have catastrophic consequences.
As device features continue to decrease in size, minimization of leakage current becomes even more important. FIGS. 4 and 5 are examples of typical OTP cells fabricated on wells of similar type. Although they are improvements over earlier structures, the fabrication process still has it challenges. The use of Vt adjust implants are required to address minimization of leakage currents. However, Vt adjust implants increase the number of process steps the memory cell is exposed to. This increase in the number of process steps exposes the memory cells to a higher probability of reliability issues. These structures also exhibit sensitivities to mask alignment issues where it would affect the functionality or reliability of the device. Finally, the differences of Vt processes between the different foundries and process nodes pose problems requiring memory cell redesigns.
The ability to control the dielectric breakdown during the programming of one time programmable (OTP) memory cells to minimize leakage current becomes more and more important as process nodes continue to decrease, as well as the need for second sourcing. Concerns of reliability, circuit density, cost and ease of manufacture will remain areas of importance. Therefore, it is highly desirable to provide an anti-fused based memory cell where; leakage current is minimized through a controlled and predictable dielectric breakdown, fabrication is done with standard processing with minimal addition of process steps, minimal sensitivity to mask alignment issues, as well as, process migration is simplified with no redesigns required. All contributing to an overall result of higher product quality and reduced costs of manufacturing.